This invention relates to a low voltage reference current generating circuit, capable of providing either a current source or current sink of a reference current which is defined by a current setting resistor.
Current generating circuits are well known in the art and in their simplest form consist of a pair of matched current mirror transistors, each having a controllable path and a control node for controlling conduction of the controllable path. In bipolar technology, the control node is the base and the controllable path is from collector to emitter. In MOS technology, the control node is the gate and the controllable path is the source/drain channel. The present invention is concerned particularly but not exclusively with bipolar technology. One of the transistors has a current setting resistor connected in its controllable path and the other transistor has its control node connected to the control node of the one transistor and also into its own controllable path. When a current flows through the current setting resistor, the same current is caused to flow in the controllable path of the other transistor and can be used to drive a suitable output transistor to sink or source a reference current related to that current through the area ratio of the output transistor and the current mirror transistors. In practical terms, the basic current mirror circuit has many limitations. One of these is that its impedance is too low for it to act as a perfect current source or sink when connected to other circuitry. To increase the impedance, it is common to include a pair of matched cascode transistors connected respectively to the current mirror transistors. Such a circuit is shown in FIG. 1a.
In FIG. 1a, references Q3 and Q4 denote a first set of matched transistors. Their bases are connected together at the connection point denoted as node 41. In addition, the base of the transistor Q3 is connected to its collector. Reference numerals Q5 and Q6 denote a second set of matched transistors. The transistor Q5 has its collector connected to the emitter of transistor Q3 and its emitter connected to ground. Its base is connected to its own collector at node 42 and to the base of transistor Q6. The transistor Q6 has its collector connected to the emitter of transistor Q4 at node 43 and its emitter connected via a current setting resistor R to ground. Reference numerals Q8 and Q7 denote output transistors connected in cascode for sinking the reference current Ir. Each output transistor has its base connected to receive the base current being injected into the transistor of the associated set (Q8 for Q3 and Q7 for Q5). The circuit is such that the reference current Ir is intended to match a current I flowing through the current setting resistor R.
Reference numerals Q1 and Q2 denote bias transistors which have their bases connected together and their emitters connected to the supply voltage Vdd. In addition, the base of the transistor Q2 is connected to its collector. The collectors of bias transistors Q1 and Q2 are connected respectively to the collectors of the first matched transistors Q3 and Q4, the latter connection being denoted as node 44.
Other known current generating circuits are illustrated for example in EP-A-155720 in the name of Philips which illustrates a cascode current source arrangement having a current mirror circuit with two current paths comprising transistors and resistors. Reference is also made to DE-C-3335379 which describes an integrated low voltage constant current source with a transistor for amplifying differential current and controlling a pair of bias transistors.
The present invention seeks to provide particularly a current source or current sink circuit which can operate down to a relatively low voltage (down to about 1.4 volts) and which has a high DC PSRR (power supply rejection ratio). The DC PSRR is defined as the ratio of the change in current source/sink reference current to the change in DC power supply.
According to the present invention there is provided a circuit for providing a reference current comprising:
first and second matched transistors each having a control node and a controllable path and connected so that with a current setting resistor in the controllable path of the second transistor, the current set in that controllable path is related to the difference in voltage characteristics between the first and second transistors and to the value of the current setting resistor;
third and fourth matched transistors each having a controllable path connected respectively to the controllable paths of the first and second transistors and their control electrodes connected together;
a set of output transistors connected in the circuit to be driven to supply said reference current in dependence on the set current; and
a fifth transistor connected in the circuit with its controllable path between a bias node related to a first supply voltage level and a node set at one voltage characteristic relative to a second supply voltage level so as to maintain the voltage across one of the third and fourth transistors at a value which is independent of the first supply voltage level thereby to reduce the magnitude of changes in the reference current as a function of the first supply voltage.
In a first embodiment the transistors are bipolar n-p-n transistors; the first supply voltage level is a positive value Vdd and the second supply voltage level is ground. The bases of the first and second transistors are connected together and the base of the first transistor is connected to its collector. The emitters of the third and fourth transistors are connected respectively to the collectors of the first and second transistors and the collector and base of the fourth transistor are connected together. With this arrangement, the base of the fifth transistor is connected to the collector of the third transistor so as to maintain the collector emitter voltage of the third transistor at a value which is independent of the supply voltage. The collector of the fifth transistor is connected to the bias node of the circuit and the emitter of the fifth transistor is connected to the bases of the first and second transistors, which are at a voltage level of one base-emitter voltage Vbe above the second supply voltage level (ground). The collector emitter voltage of the third transistor is thus held at 2 Vbe above ground and this reduces the so-called "early effect", described later.
In a second embodiment, the base of the first transistor is connected to the collector of the second transistor while the base of the second transistor is connected to the collector of the first transistor so that the first and second transistors are cross-coupled. In this embodiment, the emitter of the fifth transistor is connected to the base of the first transistor. Also, the collector of the fourth transistor is connected to its base.
In these arrangements, the early effect of the collector-emitter voltage of the fourth transistor is reduced since its collector is now connected to a point which is held at 2 Vbe above ground (Vbe of the first transistor and Vbe of the third transistor).
In the described embodiment, the bias node for the fifth transistor is provided by two bias transistors each being of opposite type to the first to fifth transistors i.e. p-n-p where the first to fifth transistors are n-p-n and having their emitters connected to the first supply voltage level and their collectors connected respectively to the collectors of the third and fourth transistors. The bases of the bias transistors are connected together to provide the bias node for the fifth transistor.
It will be appreciated that the term "matched transistors" used herein denotes transistors whose collector currents are substantially the same in the same conditions.